The list is really informational in that if some of these blocks are already in your fixed point model you don't need to swap them out with the blocks in the "Floating-Point" library to change it to a floating point model. In most of cases all you need to do is to change the input data type of the "Gateway In" blocks in the model to one of the supported floating point types and the tool will automatically generate the floating point model and netlist for simulation and implementation. The "Adder Example with all Supported Data Types" figure below shows that outputs of the same "AddSub" block are automatically adjusted to match the input data type.
PS: it is very handy to turn on the port data type display using "Format->Port/Signal Displays->Port Data Types" menu.
PPS: Click "Edit->Update Diagram" menu or pressing "CTRL-D" to update the data type display when the data types of some blocks are changed.
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| Floating Point Library in Xilinx Blockset |
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| Added Example with all Supported Data Types |
Below is a YouTube video from Xilinx on this new feature in case you are interested:
Hi Jim. Thanks for this page. I have a question. I designed a fuzzy logic controller using GUI in Simulink/Matlab environment and I want to Implement it on FPGA. I couldn't write its VHDL code. How I can implement it on FPGA using system generator tool? it is essential to mention that because fuzzy controller has not any equation to describe its basic components, I couldn't devide this to basic components. is there any way that I can use system generator for my design?
ReplyDeleteThanks
If you can't decompose your simulink model into building blocks in the Xilinx Blockset, System Generator may not be a good fit for your application. Matlab has tool called HDL Coder http://www.mathworks.com/products/hdl-coder/ that can convert Matlab functions and Simulink blocks to HDL. You may want to look into that. Once you have the HDL, you can import it to System Generator as a blackbox.
ReplyDeleteSmaller sized update patches should be made available. I use ISE 13.2(0.61xd) when i click update its > 5 GB.
ReplyDeleteHi Jim,
ReplyDeletei wanted to implement the same design with same spcifications as shown in the Xilinx Video i.e. Floating-Point FIR filter. as i am naive tos ystem generator, i could not understand how the designer has enclosed the 4-taps into the same BLUE coloured Block. I would be grateful if you can tell me, what we call it in Simulink, either top level design or instentiation?.
thanks
@Mohsin I recommend you go through the training video on System Generator below
ReplyDeletehttp://www.xilinx.com/training/free-video-courses.htm#DSP
You may also find the Xilinx DSP Tools forum useful:
http://forums.xilinx.com/t5/DSP-Tools/bd-p/DSPTOOL
Hello Jim,
ReplyDeletewhat are the FPGAs supported by Xilinx System Generator 13.3 for floating-point DSP operations?
Thanks
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