Sunday, March 25, 2012

FPGA Editor Tutorial 1: Check routability between pins

You may have seen warning messages from map or par like the one below:

Warning:LIT:683 - DSP48E1 symbol
   "Inst_mult" has one or more CE pins driven by BUFG/BUFH/BUFR. This can lead to an un-routable situation.

These warning messages make you wonder if this "un-routable situation" is due to the physical layout and/or lack of routing resources in the device or some DRC rules in the software to promote best practice. The quickest and most authoritative way to find out the answer is to check it out in FPGA Editor. Below are step-by-step instructions on how to do that using BUFG driving DSP CE pin as an example: