Saturday, June 12, 2010

Calculate OFFSET OUT value

 Let's say on your PCB you have an FPGA that sends data to a DAC like the picture below:



It's clear that you need an OFFSET OUT constraint on the FPGA data output so that the setup and hold times are met on the DAC side. The question is how to calculate the OFFSET OUT value. The best way to figure it out is to draw all clock and data signals at different points on a piece of paper and write down all propagations delays. You can then do the calculation very easily. The picture below shows clock and data signals at the DAC and FPGA:


Now let's plug in all the delay numbers:

CLK_period = 1/64MHz = 15.625ns
CLK_DELAY_PCB is about 1ns (160mm PCB trace at 1ns/6 inches)
DATA_DELAY_PCB is about 1ns (160mm PCB trace at 1ns/6 inches)
SETUP_DAC = 5.3ns

=> FPGA DATA OFFSET OUT 
= CLK period - CLK_DELAY_PCB - DATA_DELAY_PCB - SETUP_DAC 
= 15.625 - 1 - 1 - 5.3
= 8.325 ns


Tuesday, June 1, 2010

Virtex6 and Spartan6 handbooks - OBSOLETE

Now that Xilinx Document Navigator is live, I am marking this blog as OBSOLETE. I highly recommend everybody give the Xilinx Document Navigator a try. You will love it.

I always found myself having dozens of Virtex6 and Spartan6 DS/UGs open to get the information I want, so I  merged individual PDFs into one document for each family to not only reduce the cluttering on my desktop but also make search a lot easier. The handbooks can be downloaded from the links below in case somebody else may find them useful:

Download
  • Virtex-6 "Handbook": combined V6 datasheets and user guides, which are the most up-to-date versions as of Aug 4, 2010.
  • Spartan-6 "Handbook": combined S6 datasheets and user guides, which are the most up-to-date versions as of Aug 4, 2010. 

V6 handbook contents:
Name
Version
Date
DS150: Virtex-6 Family Overview
2.2
Jan 29, 2010
UG362 Virtex-6 FPGA Clocking Resources User Guide
1.5
Aug 16, 2010
UG364 Virtex-6 FPGA Configurable Logic Block User Guide
1.1
Sep 16, 2009
UG363 Virtex-6 FPGA Memory Resources User Guide
1.5
Aug 3, 2010
UG361 Virtex-6 FPGA SelectIO Resources User Guide
1.3
Aug 16, 2010
UG369 Virtex-6 FPGA DSP48E1 Slice User Guide
1.2
Sep 16, 2009
UG370 Virtex-6 FPGA System Monitor User Guide
1.1
Jun 14, 2010
UG368 Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide
1.2
Jan 17, 2010
UG366 Virtex-6 FPGA GTX Transceivers User Guide
2.4
Oct 1, 2010
UG371 Virtex-6 FPGA GTH Transceivers User Guide
2.1
Oct 4, 2010
UG373 Virtex-6 FPGA PCB Design Guide
1.2
Jun 10, 2010
UG360 Virtex-6 FPGA Configuration User Guide
3.2
Nov 1, 2010
DS152 Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
2.10
Oct 18, 2010

S6 handbook contents:


Name
Version
Date
DS160: Spartan-6 Family Overview
1.5
Aug 2, 2010
UG382 Spartan-6 FPGA Clocking Resources User Guide
1.4
Aug 24, 2010
UG384 Spartan-6 FPGA Configurable Logic Block User Guide
1.1
Feb 23, 2010
UG383 Spartan-6 FPGA Block RAM Resources User Guide
1.3
Oct 13, 2010
UG381 Spartan-6 FPGA SelectIO Resources User Guide
1.3
Mar 15, 2010
UG389 Spartan-6 FPGA DSP48A1 Slice User Guide
1.1
Aug  13, 2009
UG388 Spartan-6 FPGA Memory Controller User Guide
2.3
Aug 9,2010
UG386 Spartan-6 FPGA GTP Transceivers User Guide
2.2
Apr 30, 2010
UG393 Spartan-6 FPGA PCB Design and Pin Planning Guide
1.2
Jul 15, 2010
UG394 Spartan-6 FPGA Power Management User Guide
1.0
May 18, 2010
UG380 Spartan-6 FPGA Configuration User Guide
2.2
Jul 30, 2010
DS162 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
1.9
Aug 23, 2010