Wednesday, December 8, 2010

SysGen Example of FFT v8.0 with AXI

Starting in IDS 12.3, most, if not all, new/upgraded Xilinx IP cores will only use AXI as user interface. For FFT v8.0 specifically, it provides AXI4-Stream interfaces for input/output data and control. The AXI4-stream interface is a lot simpler than memory mapped AXI4 interface. It uses basic handshake between the master and slave as shown in the snapshot below from the FFT v8.0 Data Sheet (note that all AXI IP cores have separate data sheets than the non-AXI versions). The key thing to remember is that the AXI payload is only transferred when both TVALID and TREADY are high.

I updated the SysGen example in the blog FFT results from Matlab fft, Bit Accurate C model and SysGen FFT block with FFT v8.0 core to show the use of  AXI4 stream interface. Below is the updated SysGen model:

The updated SysGen model and m file can be downloaded from here. Again, you will need to download the bit accurate model from FFT core web site yourself to run fft_compare.m script.

Thursday, November 11, 2010

Understand maximum frequency reporting in XST

Let's say your design has a single 50MHz clock source coming in. It then goes to a DCM or PLL to generate three clock outputs at 50MHz, 100MHz and 150MHz. When you run through synthesis XST reports the maximum frequency of the design like below.

Tuesday, October 12, 2010

Use Excel to Draw Waveforms

I learned a trick yesterday from a friend's tweet that Excel can be used to draw waveforms using different cell border outlines. I just tried it out and within a few minutes I got a pretty nice waveform in front of me. There is no learning curve involved and no need to purchase and/or install a special waveform drawing tool. I presume OpenOffice Calc can be used to do the same thing.

Below is the waveform in Excel:

And here how it looks like in "Print Preview":

Thursday, July 22, 2010

DDS in System Generator: how to set up periods?

If you use DDS Compiler in System Generator, you will notice there are 4 clock periods you need to deal with (circled in red in the snapshot below). This can be confusing for first time users. Hopefully this blog can clear up some of the confusions.

  1. FPGA clock period (ns): only used for FPGA synthesis and implementation. This value does NOT affect simulation in Simulink (i.e. it will NOT affect output frequency of the DDS block).
  2. Simulink System Period: only used in Simulink simulation. This is the lowest sampling period (highest sampling frequency) among all blocks in the model. There is no significance in its absolute value as long as the sampling periods of all other blocks are multiple of the Simulink System Period. Usually it is set to 1 to keep everything simple. (e.g. every tick in a scope is 1 clock cycle).
  3. DDS System Clock (Mhz): It's used to calculate the phase increment for DDS block (see the DDS datasheet for details). Set it to match the FPGA clock period (i.e. DDS System Clock (Mhz) = 1/FPGA clock period).
  4. Explicit Sample Period: This is the sample period used for the DDS block. IMPORTANT: if you set Simulink System Period to anything other than 1, "Use explicit period" MUST be checked and "Explicit Period" set to the same value as Simulink System period. Otherwise, Simulink will use the sample period of 1 for the DDS core and the output frequency will be wrong. This is likely a bug.
 Let's use a simple model (download the model for test1 here) below to show how all these periods play together in SysGen. The clock frequency of the SineGen block is 1/100th of the Simulink System Period (or 1MHz for a 100MHz clock input).
FPGA clock period (ns) = 10
Simulink system period = 1
DDS System Clock (MHz) = 100
Use Explicit Sample Period checked and Explicit Period = 1
DDS Output (MHz) = 1

As shown in the scope below the DDS output matches the SineGen output:

FPGA clock period (ns) = 10
Simulink system period = 0.1
DDS System Clock (MHz) = 100
Use Explicit Sample Period checked and Explicit Period = 0.1
DDS Output (MHz) = 1

As shown in the scope below the DDS output matches the SineGen output. Note that the Simulink system period is now 1/10th of the period in Test1, so there are 10x more clock cycles in this test with the same simulation time.
FPGA clock period (ns) = 10
Simulink system period = 0.1
DDS System Clock (MHz) = 100
Use Explicit Sample Period unchecked
DDS Output (MHz) = 1

As shown in the scope below the DDS output frequency is 1/10th of SinGen output. The incorrect DDS output frequency is caused by that when "Use Explicit Sample Period" is unchecked Simulink use a sample period of 1 for the DDS block. So it's very important to check this checkbox and set the explicit period to match the Simulink system period if it's not 1. It's worth mentioning that for sampling frequency related issues it's very helpful to turn on "Sample Time Display" (under Format menu) and then update the diagram by pressing CTRL-D. You can easily see if the sample time used for a particular is correct with sampling time displayed on all signals.

Tuesday, July 13, 2010

FFT: Valid Values of Number of Stages Using Block RAM

If you have used the FFT block in System Generator, you probably have seen the error message below.

You've got to love these "you-did-something-wrong-but-I-am-not-gonna-tell-you-how-to-fix-it" error messages. If you read through the datasheet, you will find it's not any better as it asks you to run Core Generator to get the valid values for the FFT transform length you chose. I've gone through this quite a few times, so I put together the table below showing valid values of "Number of Stages Using Block RAM" for all supported FFT sizes (data extracted from CoreGen 12.1) for me to use it as a quick reference. I hope this will also save other people a few minutes by not having to run CoreGen to get this simple info which should have been clearly stated in the error message.

FFT SizeNumber of Stages Using Block RAM

Sunday, July 4, 2010

FFT results from Matlab fft, Bit Accurate C model and SysGen FFT block

The usage of the FFT core is straightforward, however, it does have a lot more knobs to turn compared to a simple fft() function in Matlab. Sometimes when the output from the FFT core doesn't match Matlab fft() result you start to question if there is a bug in the FFT core. I will use a simple example here hopefully to
  • provide some assurance that the result from the FFT core match well with Matlab fft() function and FFT bit accurate C model
  • provide a starting point so you can look at configurations as well as timing of control and data signals of the core in case you didn't have time to read the FFT core data sheet
Below is the SysGen model that uses a 256-point FFT with pipelined streaming IO and unscaled output in natural order. The input vector is a simple ramp (-128:127)/128 in fixed 16.15 format.
The waveform below shows the FFT signals at the beginning of the simulation in WaveScope (a great tool in Xilinx Blockset for debugging, by the way). Note that in FFT v7.0 and newer, there is no longer a requirement of 3 cycle offset between xn_index and xn_re/xn_im inputs.

The waveform below is at the end of FFT computation and data start to unload. Note that xk_index is incrementing as the core output is in natural order.

The simulation results are collected in workspace. A m script is then run to compare the results from Matlab fft(), FFT bit accurate C model, and the Simulink simulation. Below is an overlay plot showing all three outputs, where the difference is negligible.

The script also prints all elements of outputs side by side for easy comparison.

idx    Matlab       Bit Accurate SysGen
0      1.000000     1.000000     1.000000
1      81.489376    81.489504    81.489595
2      40.747756    40.747746    40.747868
3      27.168581    27.168709    27.168739
4      20.380016    20.380048    20.380078
5      16.307697    16.307667    16.307587
251    16.307697    16.307667    16.307545
252    20.380016    20.380048    20.380017
253    27.168581    27.168709    27.168495
254    40.747756    40.747746    40.747960
255    81.489376    81.489504    81.489687

In case you want to play with the example design, you can download it from here. You will need to download the bit accurate C model from FFT core web site yourself because it requires registration.

Saturday, June 12, 2010

Calculate OFFSET OUT value

 Let's say on your PCB you have an FPGA that sends data to a DAC like the picture below:

It's clear that you need an OFFSET OUT constraint on the FPGA data output so that the setup and hold times are met on the DAC side. The question is how to calculate the OFFSET OUT value. The best way to figure it out is to draw all clock and data signals at different points on a piece of paper and write down all propagations delays. You can then do the calculation very easily. The picture below shows clock and data signals at the DAC and FPGA:

Now let's plug in all the delay numbers:

CLK_period = 1/64MHz = 15.625ns
CLK_DELAY_PCB is about 1ns (160mm PCB trace at 1ns/6 inches)
DATA_DELAY_PCB is about 1ns (160mm PCB trace at 1ns/6 inches)
SETUP_DAC = 5.3ns

= 15.625 - 1 - 1 - 5.3
= 8.325 ns

Tuesday, June 1, 2010

Virtex6 and Spartan6 handbooks - OBSOLETE

Now that Xilinx Document Navigator is live, I am marking this blog as OBSOLETE. I highly recommend everybody give the Xilinx Document Navigator a try. You will love it.

I always found myself having dozens of Virtex6 and Spartan6 DS/UGs open to get the information I want, so I  merged individual PDFs into one document for each family to not only reduce the cluttering on my desktop but also make search a lot easier. The handbooks can be downloaded from the links below in case somebody else may find them useful:

  • Virtex-6 "Handbook": combined V6 datasheets and user guides, which are the most up-to-date versions as of Aug 4, 2010.
  • Spartan-6 "Handbook": combined S6 datasheets and user guides, which are the most up-to-date versions as of Aug 4, 2010. 

V6 handbook contents:
DS150: Virtex-6 Family Overview
Jan 29, 2010
UG362 Virtex-6 FPGA Clocking Resources User Guide
Aug 16, 2010
UG364 Virtex-6 FPGA Configurable Logic Block User Guide
Sep 16, 2009
UG363 Virtex-6 FPGA Memory Resources User Guide
Aug 3, 2010
UG361 Virtex-6 FPGA SelectIO Resources User Guide
Aug 16, 2010
UG369 Virtex-6 FPGA DSP48E1 Slice User Guide
Sep 16, 2009
UG370 Virtex-6 FPGA System Monitor User Guide
Jun 14, 2010
UG368 Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide
Jan 17, 2010
UG366 Virtex-6 FPGA GTX Transceivers User Guide
Oct 1, 2010
UG371 Virtex-6 FPGA GTH Transceivers User Guide
Oct 4, 2010
UG373 Virtex-6 FPGA PCB Design Guide
Jun 10, 2010
UG360 Virtex-6 FPGA Configuration User Guide
Nov 1, 2010
DS152 Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Oct 18, 2010

S6 handbook contents:

DS160: Spartan-6 Family Overview
Aug 2, 2010
UG382 Spartan-6 FPGA Clocking Resources User Guide
Aug 24, 2010
UG384 Spartan-6 FPGA Configurable Logic Block User Guide
Feb 23, 2010
UG383 Spartan-6 FPGA Block RAM Resources User Guide
Oct 13, 2010
UG381 Spartan-6 FPGA SelectIO Resources User Guide
Mar 15, 2010
UG389 Spartan-6 FPGA DSP48A1 Slice User Guide
Aug  13, 2009
UG388 Spartan-6 FPGA Memory Controller User Guide
Aug 9,2010
UG386 Spartan-6 FPGA GTP Transceivers User Guide
Apr 30, 2010
UG393 Spartan-6 FPGA PCB Design and Pin Planning Guide
Jul 15, 2010
UG394 Spartan-6 FPGA Power Management User Guide
May 18, 2010
UG380 Spartan-6 FPGA Configuration User Guide
Jul 30, 2010
DS162 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Aug 23, 2010

Sunday, April 4, 2010

Cool Programs in My Toolbox

Over years I have installed many cool little programs on my machine. They become handy for so many different things. I had to rebuild my computer recently and took me a while to google the Internet to find all the goodies. It occurred to me that it would be handy if I build a list for all these programs and put it somewhere I can easily access. And here the list goes (I will add things as I go, so it will always be work-in-progress):

Tuesday, January 12, 2010

Spartan6 Configuration Examples

The web links below will bring you directly to the block diagram for the selected configuration mode in the "Spartan6 FPGA Configuration User Guide" (UG380 v1.0 Jun 24, 2009). This is also the landing page for ADEPT (website and blog) when the "Example" button on the "Special Pin Setup" window is pressed.