Thursday, November 11, 2010

Understand maximum frequency reporting in XST

Let's say your design has a single 50MHz clock source coming in. It then goes to a DCM or PLL to generate three clock outputs at 50MHz, 100MHz and 150MHz. When you run through synthesis XST reports the maximum frequency of the design like below.

Minimum period: 6.292ns (Maximum Frequency: 158.931MHz)

Which clock is this maximum frequency reported on since the design uses all three derived clocks? Well, it depends if the derived clocks are from DCM or PLL. Let's use two test cases, one with DCM and one with PLL, to see how the maximum frequency is reported. Each test case has the same adder below in each derived clock domain.

Test case with DCM (click to download the project in IDS 12.3)
The snapshot below shows the timing summary and the worst case path for the test case with DCM. Note that the minimum period is reported as 6.292ns while the delay of the worst timing path is 2.097ns. This is because the worst case path is in the 150MHz clock domain (note that the source and destination clock of the path is clk0_i rising 3.0x) and XST references it back to the DCM input clock (clk0_i @50MHz) to calculate the maximum clock frequency. In other words, to meet the 2.097ns delay in the 150MHz clock domain, the minimum delay of the DCM input clock must be 2.097*3=6.292 ns or maximum frequency 158.93MHz. As long as the DCM input clock is 158.93MHz or lower, all the paths in all derived clock domains will meet timing.

Test case with PLL (click to download the project in IDS 12.3)
The snapshot below shows the timing summary and the worst case path for the test case with PLL. The minimum period in timing summary is the same as the delay in the worst case path. XST uses the PLL output directly to calculate the maximum frequency. Personally I think this is the wrong way of reporting the maximum frequency because users can't just change the clock frequency of one PLL output and have no way of knowing what the PLL input clock frequency needs to be. It's mostly likely an oversight (read BUG) in XST.


  1. It'd be interesting to check if the max frequency is reported correctly in case a design has both PLL and DCM.

  2. Hi, any one can explain exactly meaning of these four parameters with respect to FPGA synthesis using Xilinx ISE

    Timing Summary:
    Speed Grade: -1

    Minimum period: 1.280ns (Maximum Frequency: 781.250MHz)
    Minimum input arrival time before clock: 2.306ns
    Maximum output required time after clock: 3.259ns
    Maximum combinational path delay: No path found