Wednesday, December 8, 2010

SysGen Example of FFT v8.0 with AXI

Starting in IDS 12.3, most, if not all, new/upgraded Xilinx IP cores will only use AXI as user interface. For FFT v8.0 specifically, it provides AXI4-Stream interfaces for input/output data and control. The AXI4-stream interface is a lot simpler than memory mapped AXI4 interface. It uses basic handshake between the master and slave as shown in the snapshot below from the FFT v8.0 Data Sheet (note that all AXI IP cores have separate data sheets than the non-AXI versions). The key thing to remember is that the AXI payload is only transferred when both TVALID and TREADY are high.

I updated the SysGen example in the blog FFT results from Matlab fft, Bit Accurate C model and SysGen FFT block with FFT v8.0 core to show the use of  AXI4 stream interface. Below is the updated SysGen model:

The updated SysGen model and m file can be downloaded from here. Again, you will need to download the bit accurate model from FFT core web site yourself to run fft_compare.m script.

8 comments:

  1. ah, Xilinx doesn't allow download of bit accurate c model :/

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  2. You will need an account on xilinx.com before you can download the bit accurate model.

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  3. Hi Jim Wu
    I needed to implement a FFT processor in VHDL. I have no idea where to start with the memory interfacing stuff.. I am good in VHDL but i have no idea how to start the interfacing part.
    Its simple ADC--> RAM---> FFT--> RAM

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  4. Hi Jim Wu,

    I am using the SysGen FFT 8.0 block to implement the FFT.
    It works fine when the Target System Clock is some integer value but the block doesn't accept any real values for the same ( eg. 100 MHz is fine and not 100.5 MHz).

    Many times our sampling rates and hence system clock has to be real valued. Why then the SysGen FFT 8.0 block doesn't accept real clock values ??

    What is the way out then ?

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  5. Hi,

    Iam using XIlinx Coregen 8.0 to implement FFT for which i need to send data serially and should receive the data serially out. For that im using UART and a FIFO even. So kindly help me how to interface them all and write the code in VHDL.

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  6. Hello Dear,
    Thank you for you design, i want to implement this design in Xilinx Spartan 3An card, but i have a problem with pins (gatway in, gatway out), i want to view the result in the real scope, so can you please help me with the out pins? in the out we have a 16 bits signal so we need 16 pins or what? i am waiting for response thank you .

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  7. Hi,

    I have implemented FFT core using AXI stream interface , I am wondering how I can feed the some parameters like s_axi_config_data??!! I run the test bench and it works fine but I do not have any idea how should I stimulate the configuration parameters??

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  8. Dear Jim Wu,
    Thank you, this topic was very helpful!
    I was wondering, have you ever tried to use the clock enable port to run the core at a lower speed? In the simulink sinulation works but when I try to burn it into the fpga (virtex6) the map process fails saying that the logic block in unused and has been removed.

    Thanks,
    Luca.

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