Saturday, December 31, 2011

Memory Initialization Methods

Questions on how to initialize a ROM or RAM come up quite often on FPGA discussion boards and forums. Several methods can be used to initialize memory in RTL, during implementation, and post-implementation when targeting Xilinx FPGA devices. Some of the methods are covered in this blog.

Saturday, November 5, 2011

Rearrange Blocks in PlanAhead Schematic Viewer

The Schematic Viewer in PlanAhead is an invaluable tool to help understand and analyze synthesized netlists. PlanAhead 13.3 added a nice feature that allows users to move blocks around in the Schematic Viewer. Users can easily rearrange the schematic to follow the control/data flow or specific structure the design was intended for so they can better visualize the logic as well as use it for documentation purse.

Saturday, October 29, 2011

Use Floating License Servers

I used to just set LM_LICENSE_FILE environment variable to all floating license servers for all EDA tools that I use. It had become unacceptably slow to start and run Matlab with LM_LICENSE_FILE (see this Matlab solution for more information), so I switched to use individual environment variable that each EDA vendor checks for licenses. Things have been working a lot better since I made the change. Below is a list of environment variables that tools I run on a regular basis check for a license. This is mainly for my own reference. Hopefully somebody else may also find it useful.

Mentor Graphics: MGLS_LICENSE_FILE

P.S.: Check AR11630 ( for instructions on how to set up environment variables. My personal favorite tool for setting/editing environment variables is Rapid Environment Editor
P.P.S: Check other Cool Programs in My Toolbox

Saturday, October 22, 2011

Ternary Adder with LUT6_2

Xilinx Virtex5 and newer FPGAs have 6-input look up tables with dual outputs (LUT6_2), which can be efficiently used to build ternary adders. The technique is described in details in US patent 7274211. Below is the circuit copied from the patent filing:

Saturday, September 3, 2011

FFT Core Settings v.s Resources and Performance

Core Generator can be used to quickly find out the resource estimate, latency, and maximum throughput of the FFT core based on the current configuration of the core. This makes it very easy to do trade-off analyses between different FFT architectures, bit widths, output orders, etc.

Saturday, July 23, 2011

Set up Xilinx IDS environment for non-IDS tools

The installer for IDS 12.x or newer on Windows no longer sets up environment variables (XILINX, XILINX_EDK, PATH, etc) for running IDS tools during installation. Instead it provides a bootloader batch file that runs first to set up all required environment variables for the current session and then invokes the target application.

Sunday, April 24, 2011

IFFT with Symmetric Input in System Generator

The FFT/IFFT of real data input is symmetric: X(N-k) = X*(k). The FFT/IFFT of data with X(N-k) = X*(k) symmetry may not be real numbers unless X(0) is real and X(N/2) is real (this is implied by the symmetry equation X(N-N/2) = X*(N/2) ).

Wednesday, April 13, 2011

SysGen xlGenerateButton function example

As described in SysGen Reference Guide (view all Xilinx documents in Document Navigator), the xlGenerateButton function provides a programmatic way to invoke the System Generator code generator. The syntax is
    status = xlGenerateButton(sysgenblock)

This looks pretty straightforward: give it the full path name of the System Generator token in the design and let it run. The tricky part is that the actual name for the System Generator token has a space at the very beginning (i.e. " System Generator"), which must be included in the full path name of the SysGen token. In general, when in doubt, you can use the "gcb" function to get the full hierarchical path name of any selected block in a model. In this particular example (download the model and m script here), below are the steps to get the full path name of the System Generator token and the snapshot of the output:
  1. Open the model system_period_test 
  2. Select the System Generator token by clicking on it
  3. Go to the command window and run gcb, which will return the path name

 You can now simply start the generation by running the command below:
    xlGenerateButton('system_period_test/ System Generator')

Thursday, March 24, 2011

OFFSET Constraint Entry Methods

OFFSET IN/OUT constraints can be specified on IOs using three different methods. It can be entered
  • on specific net
  • on timing group consisting of different pads. This is the method I would recommended.
  • globally. All IOs not covered by other more specific OFFSET constraints will be included in the global OFFSET constraint.
A simple example (download the complete project with HDL and UCF here) is used below to show the syntax for these three methods and how they are reported by the Timing Analyzer:

UCF Constraints

NET "clk_i" TNM_NET = TN_clk_i;
TIMESPEC TS_clk_i = PERIOD "TN_clk_i" 20 ns HIGH 50%;

#global offset in
OFFSET = IN 10 ns BEFORE clk_i;

#offset in on time group
NET a_i[*]    TNM = TN_a_i_pads;
NET a_vld_i   TNM = TN_a_i_pads;
TIMEGRP TN_a_i_pads OFFSET = IN 8 ns BEFORE clk_i;

#add P/N of differential pairs to the same timing group
NET d_i_p     TNM = TN_d_pads;
NET d_i_n     TNM = TN_d_pads;
TIMEGRP TN_d_pads OFFSET = IN 10 ns BEFORE clk_i;

#offset in on specific net
NET "b_i[*]" OFFSET = IN 6 ns BEFORE clk_i;

Timing Result
Below is the timing result after the implementation is done.
  • Each net in the b_i bus is reported separately with 6 ns OFFSET IN requirement.
  • All nets in TN_a_i_pads group are reported under the OFFSET IN constraint on the timing group.
  • The c_i bus is not covered by any OFFSET IN constraints on specific net or timing group, so it's reported under the global OFFSET IN constraint. 
  • The differential pair d_i_p and d_i_n are reported under the same timing group.

    Friday, March 11, 2011

    OBSOLETE: Xilinx Document Navigator is Live (latest version is 1.2 as of July 26, 2011)

    This blog is OBSOLETE now that the new DocNav 2012.2 is now part of  IDS release.

    March, 2012: added a "Tips and Tricks" section.
    August, 2011: Watch Xilinx Document Navigator 1.2 Overview Video 

    Xilinx Document Navigator is an awesome document manager that
    • downloads all HW (UG, AppNotes, errata, etc) and SW documents from one "Download" button
    • automatically checks for updates on all documents
    • can easily filter, find and search all documents
    • With improvements made to "User Documents" tab in v1.2 that allow documents/URLs to be organized hierarchically and re-ordered (see the snapshot at the end), DocNav can now be used to manage ALL your documents, not just Xilinx documents. 

    Thursday, March 3, 2011

    FFT v8.0 AXI with scaled output

    The output of the FFT core can be set to "Scaled" to save some logic resources if the full precision is not required. A few things are worth mentioning to get the scaling to work: