Ternary Adder with LUT6_2

Xilinx Virtex5 and newer FPGAs have 6-input look up tables with dual outputs (LUT6_2), which can be efficiently used to build ternary adders. The technique is described in details in US patent 7274211. Below is the circuit copied from the patent filing:

This exact circuit will be automatically inferred by XST for ternary adders in RTL. Below is an example that calculates sum=x+y+z:

(* shreg_extract = "no" *) module adder (
    input clk,
    input [7:0] x ,
    input [7:0] y ,
    input [7:0] z ,
    output reg [7:0]sum
);

reg [7:0] sum_r, x_r, y_r, z_r;

always @(posedge clk) begin
    x_r <= x;
    y_r <= y;
    z_r <= z;
    sum_r <= x_r + y_r + z_r;
    sum <= sum_r;

end
endmodule

The snapshot below shows the technology view of the synthesized netlist targeting a Spartan6 device :

The MAP utilization shows exactly 8 LUTs used for the logic:
Slice Logic Utilization:
  Number of Slice Registers:                    40 out of  11,440    1%
    Number used as Flip Flops:                  40
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                         12 out of   5,720    1%
    Number used as logic:                        8 out of   5,720    1%
      Number using O6 output only:               2
      Number using O5 output only:               0
      Number using O5 and O6:                    6
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   1,440    0%
    Number used exclusively as route-thrus:      4
      Number with same-slice register load:      4
      Number with same-slice carry load:         0
      Number with other load:                    0

The two snapshots below shows the first two bits in a slice and all 4-bits packed in the same slice: