FFT Core Settings v.s Resources and Performance

Core Generator can be used to quickly find out the resource estimate, latency, and maximum throughput of the FFT core based on the current configuration of the core. This makes it very easy to do trade-off analyses between different FFT architectures, bit widths, output orders, etc.

The Implemetation Tab displays the resource estimates for DSP48 and 18Kb BRAM counts (note for device families with 36Kb BRAMs, each BRAM primitive can be used as two 18Kb BRAMs):

The Latency Tab displays the number of cycles required and the latency for the current transform length:

The numbers on the “Implementation” and “Latency” tabs are updated as soon as settings are changed on the configuration GUI. 

The table below shows the resource estimates and latency numbers for a 1024-point FFT with 250MHz clock, 16-bit inputs and outputs and different architectures and output orders:

 As shown in the table above, different settings, especially different architectures, have big impact on hardware resources and latency. One nice feature is that the tool has “Automatically Select” as an architecture option so the tool will choose the smallest implementation based on the specified “Target Data Throughput” and “Target Clock Frequency”. The selected architecture and its resource estimate and latency are displayed on the “Implementation” and “Latency” tabs (see the snapshot below).