Thursday, July 22, 2010

DDS in System Generator: how to set up periods?

If you use DDS Compiler in System Generator, you will notice there are 4 clock periods you need to deal with (circled in red in the snapshot below). This can be confusing for first time users. Hopefully this blog can clear up some of the confusions.


  1. FPGA clock period (ns): only used for FPGA synthesis and implementation. This value does NOT affect simulation in Simulink (i.e. it will NOT affect output frequency of the DDS block).
  2. Simulink System Period: only used in Simulink simulation. This is the lowest sampling period (highest sampling frequency) among all blocks in the model. There is no significance in its absolute value as long as the sampling periods of all other blocks are multiple of the Simulink System Period. Usually it is set to 1 to keep everything simple. (e.g. every tick in a scope is 1 clock cycle).
  3. DDS System Clock (Mhz): It's used to calculate the phase increment for DDS block (see the DDS datasheet for details). Set it to match the FPGA clock period (i.e. DDS System Clock (Mhz) = 1/FPGA clock period).
  4. Explicit Sample Period: This is the sample period used for the DDS block. IMPORTANT: if you set Simulink System Period to anything other than 1, "Use explicit period" MUST be checked and "Explicit Period" set to the same value as Simulink System period. Otherwise, Simulink will use the sample period of 1 for the DDS core and the output frequency will be wrong. This is likely a bug.
 Let's use a simple model (download the model for test1 here) below to show how all these periods play together in SysGen. The clock frequency of the SineGen block is 1/100th of the Simulink System Period (or 1MHz for a 100MHz clock input).
Test1:
FPGA clock period (ns) = 10
Simulink system period = 1
DDS System Clock (MHz) = 100
Use Explicit Sample Period checked and Explicit Period = 1
DDS Output (MHz) = 1

As shown in the scope below the DDS output matches the SineGen output:


Test2:
FPGA clock period (ns) = 10
Simulink system period = 0.1
DDS System Clock (MHz) = 100
Use Explicit Sample Period checked and Explicit Period = 0.1
DDS Output (MHz) = 1

As shown in the scope below the DDS output matches the SineGen output. Note that the Simulink system period is now 1/10th of the period in Test1, so there are 10x more clock cycles in this test with the same simulation time.
Test3:
FPGA clock period (ns) = 10
Simulink system period = 0.1
DDS System Clock (MHz) = 100
Use Explicit Sample Period unchecked
DDS Output (MHz) = 1

As shown in the scope below the DDS output frequency is 1/10th of SinGen output. The incorrect DDS output frequency is caused by that when "Use Explicit Sample Period" is unchecked Simulink use a sample period of 1 for the DDS block. So it's very important to check this checkbox and set the explicit period to match the Simulink system period if it's not 1. It's worth mentioning that for sampling frequency related issues it's very helpful to turn on "Sample Time Display" (under Format menu) and then update the diagram by pressing CTRL-D. You can easily see if the sample time used for a particular is correct with sampling time displayed on all signals.



34 comments:

  1. Where did the SineGen block come from? I did not find one in my library and using the 'Sine Wave' or 'Sine Wave Function' or 'DSP sine wave' blocks did not work.
    Thanks!

    ReplyDelete
  2. It's the "Sine Wave" block in Simulink->Sources. It's set up to use "Sample Based" for Sine Type.

    ReplyDelete
  3. Hi I have a virtex 4 xc4vsx35-10ff668 and I did the same step that you put there but it doesnt work, in the scope a see a line.

    Im using matlab 2010b in win 7 with the ISE suite 12.1 i dont know if thats a problem

    Thank yo

    ReplyDelete
  4. Please post a message to http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/bd-p/DSP with your model so other people can take a look at it.

    ReplyDelete
  5. Hi Jim Wu, the DDS doesn't work, do you have a basic .mdl that you can post so I can see you config?

    Thanks

    Alan

    ReplyDelete
  6. You can download the test SysGen model from https://sites.google.com/site/jimw567/home/system_period_test.mdl?attredirects=0&d=1

    ReplyDelete
  7. hi!

    what schould i change when i wanna generate a signal with frequency f=75MHz. is it possible also to generate not just one sine but more than wann with this block?

    thanks

    mary

    ReplyDelete
  8. @hf: If the system clock is higher than 150MHz, you can go to the output frequency tab of the DDS properties window and set your output to 75.

    Yes, if you want more than 1 sine wave outputs, set the "Number of Channel" to the number you want. Please note that the sampling frequency is reduce to Fsys/#_of_chan for each channel.

    ReplyDelete
  9. Hi Jim Wu,

    I am now designing a program using matlab simulink which the purpose is to simply putting a constant and convert it into binary then display it through the FRGA Xilinx Spartan-3A LED. Can you give me some idea as I wan get stuck for a long time. Sorry for being asking you here...Thanks...

    Wei Yang Chee

    ReplyDelete
  10. Hi Jim Wu,

    I am now designing a program using matlab simulink which the purpose is to simply putting a constant and convert it into binary then display it through the FRGA Xilinx Spartan-3A LED. Can you give me some idea as I wan get stuck for a long time. Sorry for being asking you here...Thanks...

    Wei Yang Chee

    ReplyDelete
  11. Please post your question with details on the problem you are getting to the DSP board on the xilinx user forum below:

    http://forums.xilinx.com/t5/DSP-Tools/bd-p/DSPTOOL

    ReplyDelete
  12. Its slow in reply which take around 2 month that why I am asking here...Anyway thanks.

    ReplyDelete
  13. Hi Jim,

    I have had a lot of confusion with the system clock rate and simulink rates when using a spectrum scope the measure the frequency. The output is different (by a factor of 10, e.g. 10MHz instead of 1MHz). Can you explain?

    I believe the Explicit period and SYG Sim sys period should be set to the same as the System DDS clock (1/100e6) to see the correct frequency on the Spectrum Scope??

    Please advise

    Email: andy.gd2712@googlemail.com

    ReplyDelete
  14. @Hacksen can you provide the link to the question that you asked on the Xilinx forum? I will take a look when I get a chance.

    ReplyDelete
  15. @andy.gd2712 Two things:

    1. When using the spectrum scope, keep in mind that the actual unit is not all that important as long as the ratio to the Fs is the same. For example, if you set up the DDS to generate a 1MHz sine wave with a 100MHz system clock, the ratio is 1:100. If you use the spectrum scope with a system period of 1 (or 1Hz), you should see a peak at 0.01Hz (10mhz or 1/100 of the system period).

    2. Spectrum scope uses FFT. Make sure the FFT length is big enough to have enough resolution to look at the signals of interest.

    ReplyDelete
  16. This comment has been removed by the author.

    ReplyDelete
  17. Hello Jim Wu,

    I'm currently at the Test2 of your tutorial and the output is not what shows on your figure.
    I do see the frequency increase on the DDS output,
    but the SinGen shows the same 2 periods of Test1.

    I get the exactly the same graph for Test3 as well. Same outputs.

    Cheers,

    Tiago

    ReplyDelete
  18. @Tiago Can you please post a message to the forum below and attach your model?

    http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/bd-p/DSP

    ReplyDelete
  19. I will do so.
    But the model I'm using is yours :)

    ReplyDelete
  20. Hi,

    I have a problem with DDS Compiler 4.0 Block of System Generator, actually it is a problem related with CORE Generator.

    Messages 13, 14 and 15 of;
    http://forums.xilinx.com/t5/DSP-Tools/hwcosim-error-on-spartan-3e-starter-kit/td-p/167302/page/2

    Did you ever faced with a problem like this?

    ReplyDelete
  21. Hi Again,

    I found the problem, it is a silly bug. I changed my regional settings to USA so the CORE Generator start working...

    ReplyDelete
  22. @Burak: great to see that you were able to figure out the problem. Thanks for posting your solution to the Xilinx forum.

    ReplyDelete
  23. @Tigao: for test2 and test3, you will need to change a few parameters in the test model in this blog. If you can post the final models for test2 and test3 to the Xilinx forum, I or somebody else can take a look to see if something is missing.

    ReplyDelete
  24. Hi Jim Wu, in new in this topic, is it possible to generate triangular signals with DDS compiler 4.0??and how to? if it is not possible could you give some advice to do it with another block?? Please...

    Thanks in advance

    ReplyDelete
  25. No, the DDS can't generate triangular signals. You can create the triangular waveform in another tool (matlab for example) and store the values in a ROM.

    ReplyDelete
  26. Hi Jim Wu,i am working on costas loop for carrier recovery of BPSK .can you plz explain how to use DDS in loop as a VCO

    ReplyDelete
  27. Raja Sekhar, You have asked Jim Wu a question which requires a very lengthy mathematics.
    I think you must read the costas loop in detail and then try this because if you understand the Costas Loop you won't have asked this question. Hope it helps for you to proceed.

    ReplyDelete
  28. i mean how to set DDS compiler 4.0 in SysGen such that i can vary output frequency according to the input phase error value.i used VCO in SIMULINK ,it worked well there but i am unable to use DDS in SysGen,when i use DDS it stays in lock for some period and coming out of lock ,again locking and this process is getting repeated. if you know how to overcome this .plz help me.
    Thanks for your response..

    ReplyDelete
  29. i mean how to set DDS compiler 4.0 in SysGen such that i can vary output frequency according to the input phase error value.i used VCO in SIMULINK ,it worked well there but i am unable to use DDS in SysGen,when i use DDS it stays in lock for some period and coming out of lock ,again locking and this process is getting repeated. if you know how to overcome this .plz help me.
    Thanks for your response..

    ReplyDelete
  30. Hi Jim Wu, i want to generate a sine wave of frequency 2MHz.
    system clock frequency is 125MHz
    phase width is 30.
    but i am not getting 2MHz as output frequency.
    Can u help me to solve this?

    ReplyDelete
  31. hi i am generating a 64 MHz sine wave using DDS compiler in system generator.
    flck=250MHz
    phase accumulator size=25 bit

    its work fine during simulation but during implementation i am unable to observe the output on LED.im using vertex5-110t board

    ReplyDelete
  32. It looks nice. I wonder what's the maximum frequency of sine wave you could generate? You mention the clock for FPGA is in ns, is it possible to generate sine wave with time resolution like 4ns or less? Any product can do that?

    ReplyDelete
  33. Hi there
    Do you know to use DDS compiler in costas loop to generate 5 mhz with fclk=100mhz?

    ReplyDelete
  34. Hello,

    Could this issue be occurring due to aliasing? Sampling period is not sufficient to capture the actual frequency.

    ReplyDelete