Sunday, March 25, 2012

FPGA Editor Tutorial 1: Check routability between pins

You may have seen warning messages from map or par like the one below:

Warning:LIT:683 - DSP48E1 symbol
   "Inst_mult" has one or more CE pins driven by BUFG/BUFH/BUFR. This can lead to an un-routable situation.

These warning messages make you wonder if this "un-routable situation" is due to the physical layout and/or lack of routing resources in the device or some DRC rules in the software to promote best practice. The quickest and most authoritative way to find out the answer is to check it out in FPGA Editor. Below are step-by-step instructions on how to do that using BUFG driving DSP CE pin as an example:

1. Run "FPGA Editor" from Windows Start menu or type "fpga_editor" from a terminal for Linux users.

2. Click the new design button, select "Design File" and "Part" on the "New" dialog window, then click "Ok" to create a new design.

3. Add a BUFG component. The quickest way is to open the "Find" dialog from "Edit" menu or pressing the shortcut "Ctrl-F" and then select "Site" for "Find What" and "BUFG*" for "Name" (note the wildcard * in the name). Click "Apply" button to bring all BUFGs to the view (see the red rectangle below). 

4. Zoom in on any BUFG site. "Zoom To Box" function or holding down CTRL and SHIFT key and using left mouse button to draw a box can be handy here. Select the BUFGCTRL and click "Add" button on the tool bar on the right side to add a new component.

5. The "Component Properties" window pops up with information on the new BUFG component. Take a note of the BUFGCTRL location (BUFGCTRL_X0Y24).

6. Repeat steps 3 to 5 to add a DSP48 component.

7. Add a net between the BUFG O pin to a DSP48 CE pin. The command line is used this time because it makes a lot easier to select a pin on a component like DSP48 with lots of inputs and outputs. Type the commands below in the command box at the bottom to select these two pins:

    select pin BUFGCTRL_X0Y24.O
    select pin DSP48_X3Y22.CEA1

8. Click "Add" button to add a net between the two pins. If the net is routable, it will be automatically routed and the routed net (in cyan) is overlaid on the routing resources used. In this case, BUFG output can be routed to DSP48 CE inputs.

9. If two pins are indeed unroutable, the net will show up as a flywire after it is added. The snapshot below shows that BUFG output can't drive another BUFG input that is too far away in VIRTEX-6.

1 comment:

  1. Jim, how would you proceed to check the routability between two flip-flops using the FPGA editor? Following your instructions, I managed to add a whole slice to the design -- but how do I activate a single flip-flop whithin that slice?

    Keep up the good work,