- The FFT block needs to be set up for IDFT by setting fwd_inv_we signal to 1 and fwd_inv signal to 0 before the start of the transform
- The FFT output needs to be manually scaled to account for the factor
**1/N**in Equation 2 above. The scaling can be done either by using the scaling schedule input or shifting the FFT output if the FFT block is set to "unscaled".

Now let's use a simple 8-point IDFT example to show how everything is put together. Below is the IDFT calculation of a test vector xn_re in Matlab:

>>xn_re=[0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8]; >>ifft(xn_re) ans = Columns 1 through 5 0.4500 -0.0500-0.1207i -0.0500-0.0500i -0.0500-0.0207i 0.0500 Columns 6 through 8 -0.0500+0.0207i -0.0500+0.0500i -0.0500+0.1207i

The idft_test simulink/sysgen model for the 8-point can be downloaded here. The model includes a block called

**WaveScope**, which is a "hidden" gem in System Generator for debugging SysGen designs, especially for hardware engineers who are used to viewing waveforms in HDL simulators.

The picture below shows the waveform at the beginning of the simulation in Wavescope. fwd_inv_we=1 and fwd_inv=0 for 1 cycle to set up the block for IDFT. Also the scale_sch is set to "010101" at the beginning to scale the FFT result down by 8 (the 1/N factor in Equation 2).

The picture below shows the waveform in Wavescope at the end of simulation, which shows that the xk_re and xk_im outputs when dv=1 match the Matlab results above when taking the quantization errors into account.

Howdy,

ReplyDeleteI am trying to follow this, but I only have Fast Fourier Transform 6.0 block available. I can't figure out where the input coming from "done" is going, as well as the input from "fwd_inv_we" is going. Could you help me out? Thanks.

Alex

i can't make the 256 IFFT.. can u tell me what parameters to change to reach it please?

ReplyDeleteWhat do you mean by "can't make the 256 IFFT"? What problems are you seeing? To make FFT core to calculate IFFT, all you need to do is to set fwd_inv to 0 before the start of transform. If you're using AXI based FFT core 8.0, check this new blog http://myfpgablog.blogspot.com/2011/04/ifft-with-symmetric-input-in-system.html for additional details.

ReplyDeletewhy you take 21 as constant for the scale_sch?

ReplyDelete21 decimal is 010101 binary, which scales down the output by 2 at each stage.

ReplyDeleteHi Jim, I have a question for you!

ReplyDeleteI'm working on LabVIEW FPGA with the same FFT block. My clock is 130Mhz and data run with a clock much smaller... Data are pushed out from a FIFO and signalled with a Input_Valid signal. Is there any PIN on the FFT block that allows to insert input data only when the Input_Valid signal is asserted ???

( I have tried to connect Input_Valid (FIFO) to Clock_Enable (FFT), but does not work because if there is no data the FFT block is in stall...

Thanks in advance

Simone C.

i have generated fft using coregen...

ReplyDeletehow to instantiate the module and what are the changes to be made to obtain the functionality of ifft

This comment has been removed by the author.

ReplyDeleteI am working on IFFT model in system generator. I already developed one model but it is showing errors.Please

ReplyDelete