Wait, what about DDR OFFSET IN/OUT using DCM clock with phase shift?

I recently wrote two blogs about DDR OFFSET constraints:

• OFFSET IN constraints for source synchronous DDR inputs
• DDR OFFSET IN/OUT constraints with DCM
  

Looks like I'm going to make a career out of talking about the OFFSET constraints on DDR IOs ;).  Here comes another one on DDR IOs clocked by DCM clock with phase shift.

The design example used here is exactly the same as in DDR OFFSET IN/OUT constraints with DCM except that a 30 degree phase shift is added to the DCM CLK0 output. The clock period in this example is 20ns, so 30 degrees phase shift translates to ~1.7ns (20ns*30/360). The timing reports on the OFFSET constraints are almost the same. The only difference is that now a ~1.7ns delay added to the time when the clock rising and falling edges.

Below are the timing reports showing the effect of the 30 degree (or 1.7ns) phase shift (highlighted in red) from the DCM:

Timing constraint: TIMEGRP "TN_ddr_in_pads" OFFSET = IN 5 ns VALID 10 ns BEFORE COMP "clk_i"         "RISING";
 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   2.718ns.
--------------------------------------------------------------------------------
Slack (setup path):     2.282ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               ddr_d_i (PAD)
  Destination:          IDDR2_inst (FF)
  Destination Clock:    clk1 rising at 1.641ns
  Requirement:          5.000ns
  Data Path Delay:      2.724ns (Levels of Logic = 2)
  Clock Path Delay:     -1.515ns (Levels of Logic = 4)
  Clock Uncertainty:    0.120ns

Timing constraint:  TIMEGRP "TN_ddr_in_pads" OFFSET = IN 5 ns VALID 10 ns BEFORE COMP "clk_i"         "FALLING";
 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   2.729ns.
--------------------------------------------------------------------------------
Slack (setup path):      2.271 ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:                ddr_d_i  (PAD)
  Destination:           IDDR2_inst  (FF)
  Destination Clock:    clk1 falling at 1.641ns
  Requirement:          5.000ns
  Data Path Delay:      2.724ns (Levels of Logic = 2)
  Clock Path Delay:     -1.526ns (Levels of Logic = 4)
  Clock Uncertainty:    0.120ns

 Timing constraint:  TIMEGRP "TN_ddr_out_pads" OFFSET = OUT 8 ns AFTER COMP "clk_i" "RISING";
 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   6.846ns.
--------------------------------------------------------------------------------
Slack (slowest paths):   1.154 ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:                ODDR2_inst  (FF)
  Destination:           ddr_d_o  (PAD)
  Source Clock:         clk1 rising at 1.641ns
  Requirement:          8.000ns
  Data Path Delay:      3.561ns (Levels of Logic = 1)
  Clock Path Delay:     1.524ns (Levels of Logic = 4)
  Clock Uncertainty:    0.120ns


Timing constraint:  TIMEGRP "TN_ddr_out_pads" OFFSET = OUT 8 ns AFTER COMP "clk_i" "FALLING";
 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   6.850ns.
--------------------------------------------------------------------------------
Slack (slowest paths):   1.150 ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:                ODDR2_inst  (FF)
  Destination:           ddr_d_o  (PAD)
  Source Clock:         clk1 falling at 1.641ns
  Requirement:          8.000ns
  Data Path Delay:      3.579ns (Levels of Logic = 1)
  Clock Path Delay:     1.510ns (Levels of Logic = 4)
  Clock Uncertainty:    0.120ns