Verilog Example (download luts_vlog.v):
(* S="TRUE" *) reg [5:0] lut_in_r;
(* LOCK_PINS="ALL", BEL="A6LUT" *)
LUT6_2 #(
.INIT (64'h0000_0000_0000_0001)
) LUT_U0 (
.I0 (lut_in_r[0]),
.I1 (lut_in_r[1]),
.I2 (lut_in_r[2]),
.I3 (lut_in_r[3]),
.I4 (lut_in_r[4]),
.I5 (1'b1 ),
.O5 (lut_out5_d ),
.O6 (lut_out6_d )
);
VHDL Example (download luts_vhd.vhd):
attribute LOCK_PINS : string;
attribute BEL : string;
attribute S : string;
attribute BEL of LUT_U0 : label is "A6LUT";
attribute LOCK_PINS of LUT_U0 : label is "ALL";
attribute S of lut_in_r : signal is "TRUE";
LUT_U0: LUT6_2
generic map (
INIT => X"0000000000000001"
)
port map (
I0 => lut_in_r(0),
I1 => lut_in_r(1),
I2 => lut_in_r(2),
I3 => lut_in_r(3),
I4 => lut_in_r(4),
I5 => '1',
O5 => lut_out5_d,
O6 => lut_out6_d
);
Set user-defined property "S = TRUE" for signal
Set user-defined property "BEL = A6LUT" for instancein unit .
Set user-defined property "LOCK_PINS = ALL" for instancein unit .
After the implementation is done, open the design in FPGA_EDITOR and check that the placement of the LUT and the pin order match the source code. Below is a snapshot of what it looks like for the example above:
Hi Jim,
ReplyDeleteI have almost the same problem. I am implementing a non-conventional circuit as follows (I am measuring LUT internal delays for different inputs..some I need this to work):
I am instantiating an LUT that implements a buffer Out=A1. The function of the LUT is not dependent on other LUT inputs. In other words,the rest of the inputs are don't cares, but I would like to keep them in my design. Here is my module:
-------------------------------------
module control(A1,Out, T);
input A1, T;
output Out;
LUT6 #(
.INIT(64'haaaaaaaaaaaaaaaa) // This implement a buffer hex a=binary 1010
) LUT6_inst (
.O(Out), // LUT general output
.I0(A1), // LUT input
.I1(T), // LUT input
.I2(T), // LUT input
.I3(T), // LUT input
.I4(T), // LUT input
.I5(T) // LUT input
);
endmodule
-------------------------------------
The rest of the inputs are being connected to each other (net "t") and controlled by another logic gate.
In my UCF file, I specify the following location constaint:
INST "LUT6_inst" LOC = "SLICE_X17Y27";
Now when the design is synthesize, I see the LUT in the RTL/Technology schematic the way I want...but what comes after MAP and PAR does not include the "T" net, which is apparently optimized out. In other word, the physical design view on FPGA editor is the LUT with only one input (A1), and there is no sign of the net "T".
More weired is that in the MAP report there is nothing any nets being removed...!
I searched a little bit and added the following MAP/Synthesis constaints but the problems still persists:
-------------------------------------
module control(A1,Out, T);
(* KEEP = "TRUE" *) (* S = "TRUE" *) input A1, T;
(* KEEP = "TRUE" *) (* S = "TRUE" *) output Out;
(* LOCK_PINS = "all" *) LUT6 #(
.INIT(64'haaaaaaaaaaaaaaaa) // Specify LUT Contents
) LUT6_inst (
.O(Out), // LUT general output
.I0(A1), // LUT input
.I1(T), // LUT input
.I2(T), // LUT input
.I3(T), // LUT input
.I4(T), // LUT input
.I5(T) // LUT input
);
endmodule
-------------------------------------
I also tried adding the following to the UCF file instead of the verilog source to no avail.
NET "T" KEEP;
NET "T" S;
I get the following message:
WARNING:Par:288 - The signal T_IBUF has no load. PAR will not attempt to route this signal.
and when i look in FPGA editot there is the LUT with only one input being used!
BTW, I am using Xilinx ISE Pack 11.4.
I would really appreciate your help!
Thanks,
Mehrdad
Why do you want to keep the inputs that are not used in LUT equation?
ReplyDeleteHi All,
ReplyDeletethis is great mini-howto but you should add a BIG-FAT-NOTE that 'map -global_opt ...' will optimize away all this lock/save magic ;)
i've checked with planahead a simple scenario:
data_i(pad) -> open-latch -> open-latch -> data_o(pad)
latches are always open: locked LUT1 (I0=gnd,INIT=X"1") drives gates.
such model survives standard mapper's optimizations (which normally optimizes open latches away) but global mapper's optimizations trims locked lut, latches and simply routes from data ibuf to obuf.
Hi Jim,
ReplyDeletewhat i am want is to keep my instantiated lut post implementation but when i am initializing my lut with 16'h0000 it shows 1 lut utilized in post synthesis but after post implementation there is only IOs in the utilization report. How do i stop the vivado to not optimize and allow to keep the LUT post optimization?... above method didnot work.