SysGen Example of FFT v8.0 with AXI

Starting in IDS 12.3, most, if not all, new/upgraded Xilinx IP cores will only use AXI as user interface. For FFT v8.0 specifically, it provides AXI4-Stream interfaces for input/output data and control. The AXI4-stream interface is a lot simpler than memory mapped AXI4 interface. It uses basic handshake between the master and slave as shown in the snapshot below from the FFT v8.0 Data Sheet (note that all AXI IP cores have separate data sheets than the non-AXI versions). The key thing to remember is that the AXI payload is only transferred when both TVALID and TREADY are high.

I updated the SysGen example in the blog FFT results from Matlab fft, Bit Accurate C model and SysGen FFT block with FFT v8.0 core to show the use of  AXI4 stream interface. Below is the updated SysGen model:

The updated SysGen model and m file can be downloaded from here. Again, you will need to download the bit accurate model from FFT core web site yourself to run fft_compare.m script.