Calculate OFFSET OUT value

 Let's say on your PCB you have an FPGA that sends data to a DAC like the picture below:

It's clear that you need an OFFSET OUT constraint on the FPGA data output so that the setup and hold times are met on the DAC side. The question is how to calculate the OFFSET OUT value. The best way to figure it out is to draw all clock and data signals at different points on a piece of paper and write down all propagations delays. You can then do the calculation very easily. The picture below shows clock and data signals at the DAC and FPGA:

Now let's plug in all the delay numbers:

CLK_period = 1/64MHz = 15.625ns

CLK_DELAY_PCB is about 1ns (160mm PCB trace at 1ns/6 inches)

DATA_DELAY_PCB is about 1ns (160mm PCB trace at 1ns/6 inches)

SETUP_DAC = 5.3ns

=> FPGA DATA OFFSET OUT 

= CLK period - CLK_DELAY_PCB - DATA_DELAY_PCB - SETUP_DAC 

= 15.625 - 1 - 1 - 5.3

= 8.325 ns