Virtex4 ODDR tristate control

The tristate control of the tristate buffer in IOB is active low. It's important to code this in RTL for the tool to correctly implement it in HW. e.g.

assign dqbit = (ts_ddrbit == 1'b0) ? out_ddrbit : 1'bz;

A code example with IDDR, ODDRs for both the data and tristate control in Virtex4 is shown below. It's tested with Xilinx IDS 11.3.

`timescale 1ns / 1ps

module tristate_oddr(
    input iddr_clk,
    input oddr_clk,
    inout dqbit,
    input ts_ddrbit1,
  input ts_ddrbit2,
  input dq_bit1,
  input dq_bit2,
 
    output test_out1,
  output test_out2
    );

wire out_ddrbit, ts_ddr_bit;

ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
    .INIT   (1'b0), // Initial value of Q: 1’b0 or 1’b1
    .SRTYPE ("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) oddr_out_ddrbit (
    .Q  (out_ddrbit), // 1-bit DDR output
    .C  (oddr_clk), // 1-bit clock input
    .CE (1'b1), // 1-bit clock enable input
    .D1 (dq_bit1), // 1-bit data input (positive edge)
    .D2 (dq_bit2), // 1-bit data input (negative edge)
    .R  (1'b0), // 1-bit reset
    .S  (1'b0) // 1-bit set
);

ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
    .INIT   (1'b0), // Initial value of Q: 1’b0 or 1’b1
    .SRTYPE ("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) oddr_ts_ddrbit (
    .Q  (ts_ddrbit), // 1-bit DDR output
    .C  (oddr_clk), // 1-bit clock input
    .CE (1'b1), // 1-bit clock enable input
    .D1 (ts_ddrbit1), // 1-bit data input (positive edge)
    .D2 (ts_ddrbit2), // 1-bit data input (negative edge)
    .R  (1'b0), // 1-bit reset
    .S  (1'b0) // 1-bit set
);


//IMPORTANT: the tristate control of the tristate buffer in IOB is active low.
assign dqbit = (ts_ddrbit == 1'b0) ? out_ddrbit : 1'bz;


IDDR #(
    .DDR_CLK_EDGE ("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
    // or "SAME_EDGE_PIPELINED"
    .INIT_Q1 (1'b0), // Initial value of Q1: 1’b0 or 1’b1
    .INIT_Q2 (1'b0), // Initial value of Q2: 1’b0 or 1’b1
    .SRTYPE  ("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_dqbit (
    .Q1 (test_out1), // 1-bit output for positive edge of clock
    .Q2 (test_out2), // 1-bit output for negative edge of clock
    .C  (iddr_clk), // 1-bit clock input
    .CE (1'b1), // 1-bit clock enable input
    .D  (dqbit), // 1-bit DDR data input
    .R  (1'b0), // 1-bit reset
    .S  (1'b0) // 1-bit set
);

endmodule

Below is what the implementation looks like in FPGA_EDITOR:

IDDR, ODDR and IOBUF:


Inside ODDR:


Inside IOB: