Showing posts with label synthesis. Show all posts
Showing posts with label synthesis. Show all posts

Saturday, December 31, 2011

Memory Initialization Methods

Questions on how to initialize a ROM or RAM come up quite often on FPGA discussion boards and forums. Several methods can be used to initialize memory in RTL, during implementation, and post-implementation when targeting Xilinx FPGA devices. Some of the methods are covered in this blog.

Thursday, November 11, 2010

Understand maximum frequency reporting in XST

Let's say your design has a single 50MHz clock source coming in. It then goes to a DCM or PLL to generate three clock outputs at 50MHz, 100MHz and 150MHz. When you run through synthesis XST reports the maximum frequency of the design like below.