OFFSET IN constraints on diff inputs ignored in IDS 11.3. Fixed in 12.4

Below is a simple test case with differential input clock and data.

`timescale 1ns / 1ps

module s3a_ibufds (
    input  clk_i_p, clk_i_n,
    input  d_i_p, d_i_n,                      
    output d_o_p, d_o_n                      
    );


wire d_in, clk_in;
reg d_r1, d_r2;

IBUFDS #(
   .IBUF_DELAY_VALUE("0"),    // Specify the amount of added input delay for
                              //    the buffer: "0"-"16" (Spartan-3A)
   .IFD_DELAY_VALUE("AUTO"),  // Specify the amount of added delay for input
                              //    register: "AUTO", "0"-"8" (Spartan-3A)
   .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
) IBUFDS_clk (
   .O  (clk_in),  // Buffer output
   .I  (clk_i_p),  // Diff_p buffer input (connect directly to top-level port)
   .IB (clk_i_n) // Diff_n buffer input (connect directly to top-level port)
);

IBUFDS #(
   .IBUF_DELAY_VALUE("0"),    // Specify the amount of added input delay for
                              //    the buffer: "0"-"16" (Spartan-3A)
   .IFD_DELAY_VALUE("AUTO"),  // Specify the amount of added delay for input
                              //    register: "AUTO", "0"-"8" (Spartan-3A)
   .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
) IBUFDS_d (
   .O  (d_in),  // Buffer output
   .I  (d_i_p),  // Diff_p buffer input (connect directly to top-level port)
   .IB (d_i_n) // Diff_n buffer input (connect directly to top-level port)
);


always @(posedge clk_in) begin
    d_r1 <= d_in;
    d_r2 <= d_r1;
end

assign d_o_p = d_r2;

endmodule

When the OFFSET IN constraints are specified with input nets,  they are simply ignored by the timing analyzer in ISE 11.3 (see UCF constraints and TA snapshot below):

NET "clk_i_p" TNM_NET = clk_i_p;
TIMESPEC TS_clk_i_p = PERIOD "clk_i_p" 20 ns HIGH 50%;
NET "d_i_p" OFFSET = IN 2 ns VALID 4 ns BEFORE "clk_i_p" RISING;
NET "d_i_n" OFFSET = IN 2 ns VALID 4 ns BEFORE "clk_i_p" RISING;

This is probably caused by a bug in TA. As a workaround, the OFFSET IN constraints can be also specified with TIMEGRP and the tool will correctly analyze the timing constraint (see the UCF constraints and TA snapshot below).
[Update Feb 10th, 2011: Verified that the bug has been fixed in IDS 12.4] The project archive can be downloaded here in case anybody is interested.

NET "clk_i_p" TNM_NET = clk_i_p;
TIMESPEC TS_clk_i_p = PERIOD "clk_i_p" 20 ns HIGH 50%; 

INST "d_i_p" TNM = TN_d_pads;
INST "d_i_n" TNM = TN_d_pads;
TIMEGRP "TN_d_pads" OFFSET = IN 2 ns VALID 4 ns BEFORE clk_i_p;