tag:blogger.com,1999:blog-419958562532914083.post5996507412396126775..comments2023-09-07T02:29:55.059-04:00Comments on Jim Wu's FPGA Blog: FFT results from Matlab fft, Bit Accurate C model and SysGen FFT blockJim Wuhttp://www.blogger.com/profile/14984103795351065801noreply@blogger.comBlogger29125tag:blogger.com,1999:blog-419958562532914083.post-54543339944346986062023-06-04T07:41:25.893-04:002023-06-04T07:41:25.893-04:00We specialize in..
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Thank you for you design, i want to i...Hello Dear, <br />Thank you for you design, i want to implement this design in Xilinx Spartan 3An card, but i have a problem with pins (gatway in, gatway out), i want to view the result in the real scope, so can you please help me with the out pins? in the out we have a 16 bits signal so we need 16 pins or what? i am waiting for response thank you .KHALED TAHKOUBIThttps://www.blogger.com/profile/14280318247068442323noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-21057656956037405692016-02-15T04:24:03.370-05:002016-02-15T04:24:03.370-05:00hello mr.jim wu
i have an error running your block...hello mr.jim wu<br />i have an error running your blockset<br />it is illegal input type on port: addr<br />Please helpppAnonymoushttps://www.blogger.com/profile/02620819216763811131noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-71263242305826561312014-04-18T07:02:28.352-04:002014-04-18T07:02:28.352-04:00Hi jim,
i m also work on fft...nd right now i m f...Hi jim,<br /><br />i m also work on fft...nd right now i m facing some problem.., can you plz help me...i have error<br /><br />ERROR:HDLCompiler:69 - "D:\temp\abc\fft33\main_prog.vhd" Line 263: is not declared.<br />ERROR:HDLCompiler:192 - "D:\temp\abc\fft33\main_prog.vhd" Line 263: Actual of formal out port shift_out cannot be an expression<br /><br /><br />what can do....i can't understand it...Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-28746842739544157202014-04-16T05:18:14.642-04:002014-04-16T05:18:14.642-04:00Hi Jim ,
I would like to try this FFT block with...Hi Jim , <br /><br />I would like to try this FFT block with analog data comming from the XADC and see what happens can you explain how we can do that because I am starting with zedboard and I am quite lost in the documentation <br /><br />Thanks Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-54991049877254804792013-02-28T05:49:24.589-05:002013-02-28T05:49:24.589-05:00please can you help meplease can you help memustafahttps://www.blogger.com/profile/10344508224362885667noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-41210186297375261832013-02-22T01:38:30.945-05:002013-02-22T01:38:30.945-05:00hi jim
i implement your design and it works well t...hi jim<br />i implement your design and it works well thanks alot but when i change the architecture from pipelined_streaming to radix_4_burst or radix-2_burst an error occure telling that an FFT block is undriven input port (The input ports on this block must be driven by other Xilinx blocks).<br />please can you help me? mustafahttps://www.blogger.com/profile/10344508224362885667noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-53424012389050882952013-01-15T09:48:41.669-05:002013-01-15T09:48:41.669-05:00Thanks. Do you know any other System Generator blo...Thanks. Do you know any other System Generator block (or Combination of blocks) that can help get the exact input frequency of a signal? I know that by using that frequency bin information I could calculate an approximation of the input frequency but what is the maximum precision I can achive with the calculation? Let say I what to calculate the input signal freq. of signals from 1MHz to 10MHz?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-36175024032730923192013-01-12T22:21:47.751-05:002013-01-12T22:21:47.751-05:00FFT doesn't tell the exact frequency of the si...FFT doesn't tell the exact frequency of the signal. FFT will tell you which frequency bin the input signal falls in.Jim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-2756327436267653422013-01-09T09:36:59.358-05:002013-01-09T09:36:59.358-05:00Jim, do you know if it possible to get the frequen...Jim, do you know if it possible to get the frequency of a signal using the FFT 7.1 output? Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-48135347888537307502012-07-28T18:41:30.540-04:002012-07-28T18:41:30.540-04:00Check http://forums.xilinx.com/t5/DSP-Tools/FFT-an...Check http://forums.xilinx.com/t5/DSP-Tools/FFT-and-IFFT-of-simple-sinusoidal-on-System-generatorr/td-p/250792Jim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-60609776182569949372012-07-26T15:03:27.753-04:002012-07-26T15:03:27.753-04:00hey JIM ...
can you pls tell me how to take a simp...hey JIM ...<br />can you pls tell me how to take a simple sinusoidal function and take its FFT and then add some phase shift in it and again take IFFT ...so that delay could be seen on scopeKashifnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-24135331566876456452011-09-24T06:28:39.983-04:002011-09-24T06:28:39.983-04:00Please post your question and/or attach your proje...Please post your question and/or attach your project to the Xilinx forum below. You will get more and faster response from the froum.<br /><br />http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/bd-p/DSPJim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-37505470645648747482011-09-23T22:53:56.566-04:002011-09-23T22:53:56.566-04:00sir,
i am running fft logicore,but in simulation...sir,<br /><br />i am running fft logicore,but in simulation i get "0" output. can u help me providing me proper testbench code of it.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-31433012946522599442011-08-06T09:05:21.509-04:002011-08-06T09:05:21.509-04:00Have you tried putting all individual files in xff...Have you tried putting all individual files in xfft_v7_1_bitacc_cmodel.zip (i.e. without nt subdirectory) in the same directory as your model? Also make sure the current working directory in Matlab is the same as your model directory. In case it helps, below are the files I have in my Matlab working directory:<br /><br />fft_compare.m<br />fft_test.mdl<br />libIp_xfft_v7_1_bitacc_cmodel.dll<br />libIp_xfft_v7_1_bitacc_cmodel.lib<br />stlport.5.1.dll<br />xfft_v7_1_bitacc_cmodel<br />xfft_v7_1_bitacc_mex.mexw32Jim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-56344214002651020582011-08-06T03:07:55.800-04:002011-08-06T03:07:55.800-04:00Great Post!
I'd love to try this on an fpga.....Great Post!<br /><br />I'd love to try this on an fpga.. using a clock output from a pll, and see if it calculates the frequency correctly! I imagine that would require some tweaking on sampling, and memory, but should be doable.<br /><br />But at the moment, I thought I'd just simulate the model project as-is, but I'm getting an error: "Error loading simulation dll fftv71_CModel". I think I have everything installed correctly.. I've unzipped the contents of xfft_v7_1_bitacc_cmodel.zip into the same folder as fft_test.mdl. As a matter of fact, I sprinkled "nt/libIp_xfft_v7_1_bitacc_cmodel.dll" all over the place including the winxp system folder, yet always get that same error. Any ideas?anonymoosenoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-72287388550811333562011-07-29T02:57:41.666-04:002011-07-29T02:57:41.666-04:00Hi
How can I change the input source and change t...Hi <br />How can I change the input source and change the fft length from 256 to smaller values. when I try to do it it is giving me an error. could you please give some comments on this? <br />Thank you,<br />MayurMayurhttps://www.blogger.com/profile/09373513265530889904noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-48823758675637611762011-07-17T01:02:06.628-04:002011-07-17T01:02:06.628-04:00You will need to download the bit accurate C model...You will need to download the bit accurate C model from FFT core web site yourself because it requires registration<br /><br />http://www.xilinx.com/products/ipcenter/FFT.htmJim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-54578423234873639752011-07-13T22:19:44.935-04:002011-07-13T22:19:44.935-04:00Hi Jim Wu, I appear to have some problems running ...Hi Jim Wu, I appear to have some problems running your code. Error message is as follows:<br /><br />??? Undefined function or method 'xfft_v7_1_bitacc_mex' for input arguments of type 'struct'.<br /><br />Error in ==> fft_compare at 32<br />[fft_ba, blkexp, overflow] = xfft_v7_1_bitacc_mex(generics, nfft, input, scaling_sch, direction);<br /><br />Can you advice on your settings/environment? My Matlab version is R2009b.<br /><br />Thanks in advanceAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-85835189972828426222011-06-18T22:15:58.964-04:002011-06-18T22:15:58.964-04:00Thanks for pointing that out. Just corrected it in...Thanks for pointing that out. Just corrected it in the blog.Jim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-89694854582818282042011-05-07T18:27:52.468-04:002011-05-07T18:27:52.468-04:00Just so you know you put "The input vector is...Just so you know you put "The input vector is a simple ramp (-128:127)/256 in fixed 16.15 format." When the input vector that you actually put in was (-128:127)/128.codyhttps://www.blogger.com/profile/12231604873603133210noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-40515754379778149982010-12-08T06:58:41.326-05:002010-12-08T06:58:41.326-05:00Please check the new blog I just posted with a Sys...Please check the new blog I just posted with a SysGen example using FFT v8.0 core. http://myfpgablog.blogspot.com/2010/12/example-of-fft-v80-with-axi.htmlJim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-86817961273104481492010-12-03T15:52:47.448-05:002010-12-03T15:52:47.448-05:00I'm having a hard time adapting this to work w...I'm having a hard time adapting this to work with Fast Fourier Transform 8.0 in SysGen 12.3.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-44804789246482687682010-08-26T02:35:11.953-04:002010-08-26T02:35:11.953-04:00I'm doing a slightly different design which in...I'm doing a slightly different design which involves DDS & FFT IP core. While generating HDL i get the following error : <br /><br />Error from hdlshared : dtconvertsl2pir: invaliddatatype<br /><br />My dds output is 10-bit. <br />Input to xn_im is via constant(simulink) double type connected to gateway_in which is signed 10-bit with 9 bit binary pt. scaling. <br /><br />Any ideas? <br /><br />Unknown data-type Fix_10_9 is the error.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-419958562532914083.post-79612575912718311942010-07-06T20:18:47.399-04:002010-07-06T20:18:47.399-04:00This is easy in FPGA. You just use dv as the enabl...This is easy in FPGA. You just use dv as the enable signal for registers or block RAMs that save the xk_re/im results.Jim Wuhttps://www.blogger.com/profile/14984103795351065801noreply@blogger.com