Virtex6 Configuration Examples

The web links below will bring you directly to the block diagram for the selected configuration mode from the "Virtex6 FPGA Configuration User Guide" (UG360 v2.0 Nov 15, 2009). This is also the landing page for ADEPT (website and blog) when the "Example" button on the "Special Pin Setup" window is pressed.

• Master Serial example
  
• Slave Serial example
• Master SPI example
• Master BPI-Up example
  
• Master BPI-Down example
  
• Master SelectMAP example
  
• Slave SelectMAP example
  
• JTAG example